The gate stack has historically been manufactured from polysilicon on a silicon dioxide or nitrided silicon oxide (SiON) gate dielectric. This gate stack is generally defined by a plasma etch process, which is known to generate post etch residuals. Following plasma etching to form the gate stack, a post gate etch clean is generally performed to remove the post etch residuals.
A conventional post gate etch clean chemistry for such a gate stack comprises sulfuric acid (H2SO4)/hydrogen peroxide (H2O2)+DI water Rinse+ammonium hydroxide and hydrogen peroxide (known as SC-1)+a DI water Rinse. Whatever gate electrode materials are not etched by the H2SO4/H2O2 treatment are generally etched by the SC-1 solution.
Recently, polysilicon has been replaced with metal and the silicon dioxide or SiON gate dielectric with a high-k dielectric material to improve transistor performance. For example, the metal gate electrode being a true electrical conductor suppresses the gate depletion layer of a MOS transistor. This changes the gate electrode/gate dielectric interface to metal on a high-k dielectric and introduces material compatibility issues that generally prevents using the conventional post gate etch clean chemistry described above.